A wafer generally goes through certain processes including deposition, etching, chemical-mechanical polishing (CMP) etc., before it is sent into a lithography scanner for exposure. Overlay errors are measured after the exposure using tools such as TWINSCAN, Archer 500 or some other appropriate device.
Lithography overlay and critical dimension uniformity (CDU) are critical parameters in semiconductor manufacturing which can adversely affect integrated circuit performance and wafer yield. Overlay errors can be caused by lithography scanner tools, mask or reticle, and process induced wafer geometry changes during scan and expose operation or other similar sources. With shrinking logic and memory device dimensions, overlay errors increasingly consume a significant fraction of the total overlay budget for critical layers. Significant efforts have been expended to identify and minimize systematic sources of overlay errors.
One method of minimizing systematic overlay errors is to use high resolution wafer geometry measurements to identify and monitor wafer fabrication processes and identify wafer geometry changes that can be fed forward to the scanner to counteract the impact of the wafer geometry changes (along with other correctible factors) during the scan and expose operation.
Analytical mechanics models, numerical finite-element models and other such methodologies have been used to make overlay predictions. However these methods suffer from the high complexity of the physical processes. Furthermore, they impact the wafer geometry that they seek to model and may not be usable to consistently predict reliable scanner corrections to counteract incoming wafer geometry changes.
Consequently, it would be advantageous if a method and apparatus existed that is suitable for consistently predicting overlay errors in a consistent wafer fabrication process and apply appropriate corrections to subsequent wafer fabrications.